1. Field of the Invention
The present invention relates to the field of integrated circuits and, more particularly, to simulation and/or modeling systems used in the design of integrated circuits.
2. Description of the Related Art
Integrated circuits (ICs), such as field programmable gate arrays (FPGAs), can be designed using High Level Modeling Systems (HLMSs). An HLMS is a software-based design tool which provides functional blocks that can be combined to build a circuit design. A block refers to a high level software-construct which represents a particular circuit function, such as multiplexing, addition, multiplication, or the like. Within an HLMS, the blocks can be arranged graphically to form a circuit.
Communication among the blocks can be represented by wires, or signals, which graphically link the blocks. Once configured, the HLMS can run various simulations upon the design. The HLMS further can generate a hardware implementation from the block representation of the circuit design. For example, an HLMS can generate the bitstream necessary to program an FPGA or can generate hardware description language (HDL) files necessary to specify the hardware design.
One advantage of using an HLMS is that such tools reduce the learning curve associated with circuit design, and particularly FPGA design. This is accomplished using a series of abstractions, such as the blocks, which effectively hide the more detailed aspects of circuit design. In illustration, when including a multiplier within an FPGA design, the designer typically is not concerned with the implementation of the multiplier itself so long as it functions properly. More than likely, it makes little or no difference whether the multiplier is implemented using a dedicated hardware resource or within the fabric of the FPGA. As such, the designer often trusts that the HLMS will make a reasonable decision as to how the multiplier will be implemented. The designer simply places a multiplier block into the circuit design and links the signals.
In some cases, however, it is useful to optimize a circuit design when using an HLMS. For example, it often is desirable to implement a circuit design using the smallest possible IC since parameters such as power consumption and cost of implementation can vary directly with the size of the IC used. To reduce size, designers must efficiently utilize circuit resources such as lookup tables, multiplexers, block RAMs, Digital Signal Processors, and the like. While an HLMS does facilitate faster circuit design and ease of use, an HLMS, by its nature, operates at a high level of abstraction which makes optimization difficult. At this level, the details of the circuit design, which are necessary for optimization, are unavailable.
To overcome this, resource estimation tools have been incorporated into HLMSs. A resource estimation tool can obtain hardware cost information such as an accounting of the hardware resources used within a circuit design. The resource estimation tool typically obtains hardware cost information from a more sophisticated circuit analysis tool such as a mapper. In any case, resource estimation tools available within conventional HLMSs lack a graphical interface and, instead, provide only a text-based listing of the various circuit resources used. The text display can be less than intuitive, making it difficult for designers to quickly interpret data. Tools that do provide the necessary detail for optimizing a circuit design and present that information in a more intuitive manner usually operate at a much lower level. As such, these tools tend to have higher learning curves and do not support the fast and efficient design methodologies that have come to be associated with an HLMS.
It would be beneficial to present information relating to the hardware costs of a circuit design in a graphical and intuitive manner, while still providing the ease of use and high level operation typically associated with an HLMS.